1. Field of the Invention
This invention is related to the field of SMP and CMT, and particularly to a system for implementing SMP with CMTs.
2. Description of the Related Art
Chip multithreading (CMT) has been proposed as one way to utilize the transistors that can now be integrated on the same semiconductor substrate, or integrated circuit chip. Particularly, one or more processor cores may be included on a chip, and each processor core is multithreaded. That is, the processor core includes hardware to have multiple threads active. Software can activate the threads for execution, and the hardware handles executing the threads, interleaving access among the instructions from different threads to shared processor core hardware, etc.
Prior to the advent of multithreading, executing more than one thread concurrently required multiple single-threaded processors. Each processor is a separate chip, and the processors are connected in some fashion to memory. For example, in the symmetric multiprocessing (SMP) model, processors are considered equals and any processor can execute any thread (or process). Typically, cache coherency (or more briefly, coherency) is maintained to ensure that memory accesses from different processors occur in a coherent fashion (e.g. the most recently updates to bytes at a given address are delivered in response to a read of the given address).
One SMP implementation is a multidrop bus to which each single-threaded processor chip is connected. An address transmitted on the bus (e.g. by one of the processors) is snooped by the other processors, which check their caches for a copy of the data being accessed. In other implementations, explicit probe transactions (or inquire transactions) are transmitted on the bus and only the probe addresses are snooped against the cache.
The multidrop SMP bus is generally not suitable for handling multiple CMTs. The multidrop bus is highly capacitive, which generally means that the bus clock cycle is relatively long. The bandwidth and latency on the bus is thus limited. CMTs, executing multiple threads/processes and thus generating numerous memory accesses to many different addresses, would exceed the available bandwidth and the latency would reduce performance. Additionally, CMTs that include multiple processor cores would not be able to maintain coherency using the multidrop bus. Another method used to interconnect single-threaded processors is the point-to-point interconnect of Hypertranspor™ and the like.